The evolution of dual gate technology in integrated circuit (IC) devices has evolved from having doped polycrystalline gates resting on different gate oxide thicknesses to introduction of different metal gates lying over high k dielectrics. Owing to an alteration in work function from the changing oxide thickness and different metals, devices on the same chip can operate by different voltages. However, the polycrystalline gates can suffer from depletion effects as oxides grow thinner, especially for the case of implanted n-doped gates. For the thinner oxides, reliability and integrity also pose serious concerns.
Some means to resolve these problems will be to use metal gates, in-situ p- or n-doped poly gates (minimum poly depletion effects) and high-k dielectrics. Preferably, the initial intention of having different work function can be accomplished by varying gate electrodes rather than changing oxide thickness.
U.S. Pat. No. 5,236,872 to van Ommen et al. describes a process of forming a silicide layer in a poly layer by a metal ion implantation (I/I) and anneal.
U.S. Pat. No. 6,043,157 to Gardner et al. describes a process of forming a semiconductor device having dual gate electrode material.
U.S. Pat. No. 5,122,479 to Audet et al. describes a method of manufacturing a semiconductor device comprising a silicide layer.
U.S. Pat. No. 6,087,236 to Chau et al. describes a method of making an integrated circuit with multiple gate dielectric structures.